Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs
暂无分享,去创建一个
[1] Souvik Mahapatra,et al. CHISEL flash EEPROM. II. Reliability , 2002 .
[2] R. K. Smith,et al. Monte Carlo simulation of the CHISEL flash memory cell , 2000 .
[3] M.R. Pinto,et al. Secondary Electron flash-a high performance, low power flash technology for 0.35 /spl mu/m and below , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[4] Guido Torelli,et al. Multilevel Flash Memories , 1999 .
[5] M. Mastrapasqua. Low voltage flash memory by use of a substrate bias , 1999 .
[6] Piero Olivo,et al. Flash memory cells-an overview , 1997, Proc. IEEE.
[7] Souvik Mahapatra,et al. CHISEL flash EEPROM. I. Performance and scaling , 2002 .
[8] A. Frommer,et al. EEPROM/flash sub 3.0 V drain-source bias hot carrier writing , 1995, Proceedings of International Electron Devices Meeting.
[9] M. Lanzoni,et al. Nonvolatile multilevel memories for digital applications , 1998, Proc. IEEE.