Performance Impact of TLB on the K computer Applications

Application performance in high-performance computing depends on various factors such as algo- rithms and systems. To maximize hardware performance, it is important for collaboration among hardware, system software, and application developers. We report the performance impact of TLB on the application by simultaneously running several applications on the K computer. TLB is a mechanism that translates virtual and physical addresses in any architecture. Performance impact of TLB on the application is predicted by the data access pattern, which is similar to that of the cache. It is difficult to analyze when and where a TLB miss may occur, because it is often measured not only as performance degradation but also as performance fluctuation. In this paper, we discuss not only calculation results based on some applications that measure the performance impact by TLB misses but also their causes and characteristics, as well as some ways to resolve them.