Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding

Non-Surjective Finite Alphabet Iterative Decoding (NS-FAID) represents an LDPC decoding algorithm that uses reduced message storage, with similar or improved error correction performance with respect to Min-Sum. In this paper, we employ NS-FAID compression tables for a memory-centric flooded LDPC decoding architecture. Due to the approximate message storage, improved memory footprint and overall cost is obtained using the NS-FAID approach. We present FPGA synthesis results, in terms of LUT-FF pairs used, working frequency and throughput, as well as Throughput to Area Ratio (TAR). The estimates indicate that employing NS-FAID compression tables yield improvements between 25% and 110% in TAR with respect to the baseline Min-Sum decoder.

[1]  Sridhar Rajagopal,et al.  Low-power dual quantization-domain decoding for LDPC codes , 2014, 2014 IEEE Global Communications Conference.

[2]  Chang-Ming Lee,et al.  Optimization of memory utilization for partially parallel QC-LDPC decoder , 2010, 2010 International Symposium On Information Theory & Its Applications.

[3]  Ieee Microwave Theory,et al.  Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems — Amendment for Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands , 2003 .

[4]  David Declercq,et al.  Non-surjective finite alphabet iterative decoders , 2016, 2016 IEEE International Conference on Communications (ICC).

[5]  Manabu Hagiwara,et al.  Comment on "Quasi-Cyclic Low Density Parity Check Codes From Circulant Permutation Matrices" , 2009, IEEE Trans. Inf. Theory.

[6]  Valentin Savin,et al.  Unrolled layered architectures for non-surjective finite alphabet iterative decoders , 2017, 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

[7]  Brendan J. Frey,et al.  Iterative Decoding of Compound Codes by Probability Propagation in Graphical Models , 1998, IEEE J. Sel. Areas Commun..

[8]  David Declercq,et al.  High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders , 2017, 2017 IEEE International Conference on Communications Workshops (ICC Workshops).

[9]  Shu Lin,et al.  Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Zhongfeng Wang,et al.  Area-efficient parallel decoder architecture for high rate QC-LDPC codes , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[11]  Zhongfeng Wang,et al.  A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Hideki Imai,et al.  Reduced complexity iterative decoding of low-density parity check codes based on belief propagation , 1999, IEEE Trans. Commun..

[13]  Robert Michael Tanner,et al.  A recursive approach to low complexity codes , 1981, IEEE Trans. Inf. Theory.

[14]  Nanning Zheng,et al.  LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives , 2013, FAST.