Quantum circuit physical design flow for the multiplexed trap architecture

Abstract Physical design is the second process in the design flow of quantum circuits that receives a netlist as input and generates a layout at a target technology. Quantum physical design problem is intractable. This process tackles the operation scheduling, placement, and qubit routing problems. Some approaches have been proposed for the physical design in ion trap technology that is currently one of the most advanced quantum technologies. These methods do not use all capabilities of the technology. Focusing on this issue, in this paper, a physical design flow is proposed for the multiplexed trap architecture utilizing the capabilities provided by the technology not considered by other approaches to improve the latency and area metrics. Experimental results show that the proposed approach decreases the average latency of quantum circuits by about 39.5% for the attempted benchmarks.

[1]  Robert M. Jopson,et al.  System design for large-scale ion trap quantum information processor , 2005, Quantum Inf. Comput..

[2]  D. Leibfried,et al.  Towards a scalable quantum computer/simulator based on trapped ions , 2004 .

[3]  Malgorzata Marek-Sadowska,et al.  Pre-layout physical connectivity prediction with application in clustering-based placement , 2005, 2005 International Conference on Computer Design.

[4]  C. Monroe,et al.  Architecture for a large-scale ion-trap quantum computer , 2002, Nature.

[5]  Morteza Saheb Zamani,et al.  Quantum circuit physical design methodology with emphasis on physical synthesis , 2014, Quantum Inf. Process..

[6]  King,et al.  Demonstration of a fundamental quantum logic gate. , 1995, Physical review letters.

[7]  J. Hughes,et al.  Transport of Quantum States and Separation of Ions in a Dual Rf Ion Trap * , 2002 .

[8]  T. Monz,et al.  Realization of the quantum Toffoli gate with trapped ions. , 2008, Physical review letters.

[9]  Li-Da Huang,et al.  Redundant-via enhanced maze routing for yield improvement , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[10]  John Kubiatowicz,et al.  Automated generation of layout and control for quantum circuits , 2007, CF '07.

[11]  R. Feynman Quantum mechanical computers , 1986 .

[12]  Wolfgang Lange,et al.  Quantum Computing with Trapped Ions , 2009, Encyclopedia of Complexity and Systems Science.

[13]  Christof Zalka Simulating quantum systems on a quantum computer , 1996, Proceedings of the Royal Society of London. Series A: Mathematical, Physical and Engineering Sciences.

[14]  Mark Oskin,et al.  An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures , 2005, ISCA 2005.

[15]  Morteza Saheb Zamani,et al.  GATE LOCATION CHANGING: AN OPTIMIZATION TECHNIQUE FOR QUANTUM CIRCUITS , 2012 .

[16]  D. Wineland,et al.  A 303-MHz frequency standard based on trapped Be/sup +/ ions , 1990 .

[17]  Alireza Shafaei,et al.  Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits , 2014, Quantum Information Processing.

[18]  Frederic T. Chong,et al.  Building quantum wires: the long and the short of it , 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..

[19]  Morteza Saheb Zamani,et al.  A hierarchical layout generation method for quantum circuits , 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

[20]  Massoud Pedram,et al.  Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[21]  Pedram Khalili Amiri,et al.  Quantum computers , 2003 .

[22]  Elad Hazan,et al.  O(sqrt(log(n)) Approximation to SPARSEST CUT in Õ(n2) Time , 2004, SIAM J. Comput..

[23]  Andrew W. Cross,et al.  A quantum logic array microarchitecture: scalable quantum data movement and computation , 2005, 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05).

[24]  John Kubiatowicz,et al.  A fault tolerant, area efficient architecture for Shor's factoring algorithm , 2009, ISCA '09.

[25]  L. Deslauriers,et al.  T-junction ion trap array for two-dimensional ion shuttling, storage, and manipulation , 2005, quant-ph/0508097.

[26]  Todd A. Brun,et al.  Quantum Computing , 2011, Computer Science, The Hardware, Software and Heart of It.

[27]  Morteza Saheb Zamani,et al.  Auxiliary qubit selection: a physical synthesis technique for quantum circuits , 2011, Quantum Inf. Process..

[28]  Morteza Saheb Zamani,et al.  A quantum physical design flow using ILP and graph drawing , 2013, Quantum Inf. Process..

[29]  D. Leibfried,et al.  Quantum state manipulation of trapped atomic ions , 1998, Proceedings of the Royal Society of London. Series A: Mathematical, Physical and Engineering Sciences.

[30]  Lov K. Grover A fast quantum mechanical algorithm for database search , 1996, STOC '96.

[31]  Nisheeth K. Vishnoi,et al.  On partitioning graphs via single commodity flows , 2008, STOC.

[32]  Carlo Batini,et al.  Automatic graph drawing and readability of diagrams , 1988, IEEE Trans. Syst. Man Cybern..

[33]  Mark Oskin,et al.  QUALE: quantum architecture layout evaluator , 2005, SPIE Defense + Commercial Sensing.

[34]  Peter W. Shor,et al.  Polynomial-Time Algorithms for Prime Factorization and Discrete Logarithms on a Quantum Computer , 1995, SIAM Rev..

[35]  Boris B. Blinov,et al.  Sympathetic Cooling of Trapped Cd , 2002 .

[36]  F. Schmidt-Kaler,et al.  Quantum computing with trapped ions , 2008, 0809.4368.

[37]  J. Cirac,et al.  Quantum Computations with Cold Trapped Ions. , 1995, Physical review letters.

[38]  J. Britton,et al.  Sympathetic cooling of 9 Be + and 24 Mg + for quantum logic , 2003 .

[39]  L. Deslauriers,et al.  Sympathetic cooling of trapped Cd + isotopes , 2002 .

[40]  Morteza Saheb Zamani,et al.  Improving Latency of Quantum Circuits by Gate Exchanging , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[41]  Frederic T. Chong,et al.  Scheduling physical operations in a quantum information processor , 2006, SPIE Defense + Commercial Sensing.

[42]  John Kubiatowicz,et al.  Running a Quantum Circuit at the Speed of Data , 2008, 2008 International Symposium on Computer Architecture.

[43]  C. Monroe,et al.  Scaling the Ion Trap Quantum Processor , 2013, Science.

[44]  Morteza Saheb Zamani,et al.  Quantum physical synthesis: Improving physical design by netlist modifications , 2010, Microelectron. J..

[45]  Alireza Shafaei,et al.  Squash: a scalable quantum mapper considering ancilla sharing , 2014, GLSVLSI '14.

[46]  A. G. Fowler,et al.  Two-dimensional architectures for donor-based quantum computing , 2006 .

[47]  Mark Oskin,et al.  Microcoded Architectures for Ion-Tap Quantum Computers , 2008, 2008 International Symposium on Computer Architecture.

[48]  Mechthild Stoer,et al.  A simple min-cut algorithm , 1997, JACM.