A High-Throughput Binary Arithmetic Coding Architecture for H.264/AVC CABAC
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[1] H. Shojania,et al. A high performance CABAC encoder , 2005, The 3rd International IEEE-NEWCAS Conference, 2005..
[2] Javier D. Bruguera,et al. High-Throughput Architecture for H.264/AVC CABAC Compression System , 2006, IEEE Transactions on Circuits and Systems for Video Technology.
[3] Ajay Luthra,et al. Overview of the H.264/AVC video coding standard , 2003, IEEE Trans. Circuits Syst. Video Technol..
[4] Heiko Schwarz,et al. Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard , 2003, IEEE Trans. Circuits Syst. Video Technol..
[5] Atila Alvandpour,et al. A 130-nm 6-GHz 256 /spl times/ 32 bit leakage-tolerant register file , 2002 .
[6] Xiaohua Tian,et al. Full RDO-Support Power-Aware CABAC Encoder With Efficient Context Access , 2009, IEEE Transactions on Circuits and Systems for Video Technology.
[7] Wei Zheng,et al. Efficient pipelined CABAC encoding architecture , 2008, IEEE Transactions on Consumer Electronics.
[8] Yong-Surk Lee,et al. A Novel Architecture for High Performance CABAC Encoder , 2006 .
[9] Youn-Long Lin,et al. A Hardwired Context-Based Adaptive Binary Arithmetic Encoder for H. 264 Advanced Video Coding , 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
[10] Grzegorz Pastuszak. A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC , 2008, IEEE Transactions on Circuits and Systems for Video Technology.
[11] Hassan Shojania,et al. A VLSI architecture for high performance CABAC encoding , 2005, Visual Communications and Image Processing.
[12] Rajiv V. Joshi,et al. A 500-MHz, 32-word/spl times/64-bit, eight-port self-resetting CMOS register file , 1999 .