The cost of quality: Reducing ASIC defects with I/sub DDQ/, at-speed testing, and increased fault coverage

This paper attempts to quantify the economic benefits of including improved design for test (DFT) strategies into the ASIC design process. The qualitative results of higher stuck-at fault coverage, I/sub DDQ/ testing, and BIST, have been documented; the quantitative results and their economic impact have not. This paper presents real life costs associated with poor quality in order to justify the resource investments needed to support improved DFT strategies.<<ETX>>