Low Latency Approximate Adder for Highly Correlated Input Streams

Approximate computing helps achieve better performance or energy efficiency by trading accuracy. Most approximate adders are composed of multiple sub-adders and long carry chains are split to reduce latency, thus benefiting from the fact that carry propagation across long carry chains is rare for uniformly distributed inputs. One key tradeoff of these approximate adders is between latency and error rate. The more prediction bits are used, the lower is the error rate, but the latency is longer. In this paper, we present a Correlation Aware Predictor (CAP) which utilizes spatial-temporal correlation information of input streams to predict carry-in value for sub-adders. CAP uses less prediction bits which help reduce adder latency significantly. For highly correlated input streams, we found that CAP can reduce adder latency by about 23% at the same error rate compared to prior work. We implemented a CAP-based approximate adder in Verilog and synthesized with TSMC 16nm library. Synthesis results show that CAP-based adder can reduce latency by 25% and save 13% in silicon area compared to state-of-the-art.

[1]  Peter J. Varman,et al.  High performance reliable variable latency carry select addition , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Davide De Caro,et al.  Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs , 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

[3]  Nikolaos Hardavellas,et al.  VaLHALLA: Variable Latency History Aware Local-carry Lazy Adder , 2017, ACM Great Lakes Symposium on VLSI.

[4]  Jie Han,et al.  Approximate computing: An emerging paradigm for energy-efficient design , 2013, 2013 18th IEEE European Test Symposium (ETS).

[5]  Zhiru Zhang,et al.  CASA: Correlation-aware speculative adders , 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[6]  Gang Wang,et al.  Enhanced low-power high-speed adder for error-tolerant application , 2009, 2010 International SoC Design Conference.

[7]  Fabrizio Lombardi,et al.  An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders , 2015, IEEE Transactions on Computers.

[8]  Kaushik Roy,et al.  Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications , 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

[9]  Andrew B. Kahng,et al.  Accuracy-configurable adder for approximate arithmetic designs , 2012, DAC Design Automation Conference 2012.

[10]  Kaushik Roy,et al.  Analysis and characterization of inherent application resilience for approximate computing , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Paolo Ienne,et al.  Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design , 2008, 2008 Design, Automation and Test in Europe.

[12]  Rakesh Kumar,et al.  On reconfiguration-oriented approximate adder design and its application , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[13]  Román Hermida,et al.  Multispeculative Addition Applied to Datapath Synthesis , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Muhammad Shafique,et al.  Probabilistic Error Modeling for Approximate Adders , 2017, IEEE Transactions on Computers.

[15]  Muhammad Shafique,et al.  A low latency generic accuracy configurable adder , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).