Timing-Driven Routing of High Fanout Nets

It has been observed in the past that the PathFinder routing algorithm runtime could be hampered by high fan out nets, primarily due to the time spent on the initialization of the priority queue. However, a solution has only been reported for routability/wirelength driven routers. In this paper, we report two heuristics that address the same issue for timing-driven routers. We show that on standard MCNC benchmarks, the proposed techniques can achieve 1.53 and 1.56 time speed up against the versatile placement and router (VPR), while achieving the same quality of result.

[1]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[2]  Martine D. F. Schlag,et al.  New parallelization and convergence results for NC: a negotiation-based FPGA router , 2000, FPGA '00.

[3]  Marcel Gort,et al.  Deterministic multi-core parallel routing for FPGAs , 2010, 2010 International Conference on Field-Programmable Technology.

[4]  Vaughn Betz,et al.  High-quality, deterministic parallel placement for FPGAs on commodity hardware , 2008, FPGA '08.

[5]  Malgorzata Marek-Sadowska,et al.  An efficient router for 2-D field programmable gate array , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[6]  Guy G.F. Lemieux A Detailed Routing Algorithm for Allocating Wire Segments in Field-Programmable Gate Arrays , 1998 .

[7]  Jianwen Zhu,et al.  Parallelizing Simulated Annealing-Based Placement Using GPGPU , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[8]  Russell Tessier Negotiated A* Routing for FPGAs ∗ , 1998 .

[9]  Jianwen Zhu,et al.  Towards scalable placement for FPGAs , 2010, FPGA '10.

[10]  Carl Ebeling,et al.  Placement and routing tools for the Triptych FPGA , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Jonathan Rose,et al.  A detailed router for field-programmable gate arrays , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[12]  Guy Lemieux,et al.  Scalable and deterministic timing-driven parallel placement for FPGAs , 2011, FPGA '11.

[13]  Vaughn Betz,et al.  A fast routability-driven router for FPGAs , 1998, FPGA '98.