Digital On-Chip Calibration of Analog Systems towards Enhanced Reliability

This chapter deals with digital method of calibration for analog integrated circuits as a means of extending its lifetime and reliability, which consequently affects the reliability the analog electronic system as a whole. The proposed method can compensate for drift in circuit’s electrical parameters, which occurs either in a long term due to aging and electrical stress or it is rather more acute, being caused by process, voltage and temperature variations. The chapter reveals the implementation of ultra-low voltage on-chip system of digitally calibrated variable-gain amplifier (VGA), fabricated in CMOS 130 nm technology. It operates reliably under supply voltage of 600mV with 10% variation, in temperature range from −20°C to 85°C. Simulations suggest that the system will preserve its parameters for at least 10 years of operation. Experimental verification over 10 packaged integrated circuit (IC) samples shows the input offset voltage of VGA is suppressed in range of 13μV to 167μV. With calibration the VGA closely meets its nominally designed essential specifications as voltage gain or bandwidth. Digital calibration is comprehensively compared to its widely used alternative, Chopper stabilization through its implementation for the same VGA.

[1]  Marvin Onabajo,et al.  Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip , 2012 .

[2]  G. Ghibaudo,et al.  Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing , 2020, 2020 IEEE Symposium on VLSI Technology.

[3]  Paul Ampadu,et al.  Managing Temperature Effects in Nanoscale Adaptive Systems , 2011 .

[4]  Minghua Tang,et al.  A Continuously and Widely Tunable 5 dB-NF 89.5 dB-Gain 85.5 dB-DR CMOS TV Receiver With Digitally-Assisted Calibration for Multi-Standard DBS Applications , 2013, IEEE Journal of Solid-State Circuits.

[5]  Pui-In Mak,et al.  On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Marc Pastre,et al.  Methodology for the digital calibration of analog circuits and systems using sub-binary radix DACs , 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

[7]  A. Toffoli,et al.  Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond , 2010, 2010 Symposium on VLSI Technology.

[8]  Youming Zhang,et al.  A 250MHz 60dB gain control range 1dB gain step programmable gain amplifier with DC-offset calibration , 2015, 2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

[9]  D. Nikolov,et al.  Study of Process Variability-Sensitive Local Device Parameters for 14-nm Bulk FinFETs , 2020, Information Security Solutions Europe.

[10]  M. Kayal,et al.  An automatic offset compensation technique applicable to existing operational amplifier core cell , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[11]  Zhih-Siou Cheng,et al.  A CMOS Variable Gain Amplifier with DC Offset Calibration Loop for Wireless Communications , 2006, 2006 International Symposium on VLSI Design, Automation and Test.

[12]  Foster F. Dai,et al.  A CMOS programmable gain amplifier with a novel DC-offset cancellation technique , 2010, IEEE Custom Integrated Circuits Conference 2010.

[13]  Hal Edwards,et al.  Device physics origin and solutions to threshold voltage fluctuations in sub 130 nm CMOS incorporating halo implant , 2010, 2010 IEEE Dallas Circuits and Systems Workshop.

[14]  Ziyad Al Tarawneh.  The effects of process variations on performance and robustness of bulk CMOS and SOI implementations of C-elements , 2011 .