A flexible, fully configurable architecture for MPEG-2 video encoding

This paper introduces a video encoder architecture for real-time MPEG-2 Main Profile at Main Level (MP@ML) encoding. It combines a programmable CPU for controlling with a fully configurable, but dedicated compression core. Therefore the encoder architecture offers great processing flexibility at a high computational performance. One focal point of the paper is the motion estimation unit of the compression core that employs a highly efficient recursive block-matching motion estimation algorithm. To guarantee full memory bandwidth utilization, the number of candidate blocks used for the block-matching process can be varied. The compression core was implemented in a 0.18 /spl mu/m 5 ML CMOS technology to run at 54 MHz. The architecture was thoroughly verified using hardware/software co-simulation.