暂无分享,去创建一个
Michael J. Butler | John Colley | Ashish Darbari | Iain Singleton | M. Butler | A. Darbari | J. Colley | Iain Singleton
[1] Samin Ishtiaq,et al. Reasoning about the ARM weakly consistent memory model , 2008, MSPC '08.
[2] Michael J. Butler,et al. ProB: an automated analysis toolset for the B method , 2008, International Journal on Software Tools for Technology Transfer.
[3] Thai Son Hoang,et al. Rodin: an open toolset for modelling and reasoning in Event-B , 2010, International Journal on Software Tools for Technology Transfer.
[4] Michel Dubois,et al. Memory access buffering in multiprocessors , 1998, ISCA '98.
[5] Larry Rudolph,et al. Commit-reconcile & fences (CRF): a new memory model for architects and compiler writers , 1999, ISCA.
[6] Jade Alglave,et al. Fences in Weak Memory Models , 2010, CAV.
[7] Rajeev Alur,et al. An Axiomatic Memory Model for POWER Multiprocessors , 2012, CAV.
[8] Jade Alglave,et al. Herding cats: modelling, simulation, testing, and data-mining for weak memory , 2014, PLDI 2014.
[9] Francesco Zappa Nardelli,et al. x86-TSO , 2010, Commun. ACM.
[10] Arvind,et al. Memory Model = Instruction Reordering + Store Atomicity , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).
[11] Paul E. McKenney. Memory ordering in modern microprocessors, Part I , 2005 .
[12] Vaughan R. Pratt,et al. Modeling concurrency with partial orders , 1986, International Journal of Parallel Programming.
[13] Anoop Gupta,et al. Memory consistency and event ordering in scalable shared-memory multiprocessors , 1990, ISCA '90.
[14] Anoop Gupta,et al. Memory consistency and event ordering in scalable shared-memory multiprocessors , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[15] Paul E. McKenney. Memory ordering in modern microprocessors, Part II , 2005 .
[16] Leslie Lamport,et al. How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs , 2016, IEEE Transactions on Computers.