Soft error improvement of dynamic RAM with Hi-C structure

A novel Hi-C RAM cell is proposed for reducing the alpha-particle-induced soft error rate. The novel cell utilizes the doubly-implanted Hi-C struture combined with the boosted storage gate, which provides much alignment tolerance to the implantation steps for the Hi-C cell. This Hi-C cell having a charge storage capacity 30% larger than that of the conventional cell results in one order of magnitude decrease in soft errors as compared with the conventional one. The concept of this excellent cell is successfully demonstrated by a 64K dynamic RAM fabricated on the basis of a 3 pm design rule. Experimental results on refresh time of the 64K dynamic RAM indicates that the Hi-C cell has been realized without defective effects on the leakage of the stored charge.