In recent years the demand has surged for low-power and small form-factor wireless communications devices. Coupled with the migration of desktop computing to mobile computing, a new market is merging for portable products that combine wireless communications and high-performance computing. The evolution of semiconductor device technology toward the deep submicron regime is enabling the development of CMOS RF communications circuits which are amenable to monolithic integration with existing mixed-signal processes. A 1.2- micron bulk CMOS process has been used to develop a monolithic architecture consisting of an 8-bit RISC microprocessor, a 256-byte SRAM memory, power management, and a 400-MHz RF transceiver. The logic portion of the IC operates at 50 MHz, and the RF transceiver achieves a data transmission rate of 16 kb/sec with a 10 kHz bandwidth. On- chip power regulation minimizes supply glitches due to logic switching, and power management is provided to minimize the standby power dissipation of idle components. This IC demonstrates the potential of CMOS to deliver a low-power architecture for computing and wireless communication.
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