A hybrid DBNS processor for DSP computation

This paper introduces a modification to an index calculus representation for the double-base number system (DBNS). The DBNS uses the bases 2 and 3; it is redundant (very sparse) and has a simple two-dimensional representation. An extremely sparse form of the DBNS uses a single non-zero digit to represent any real number with arbitrary precision. In this case the single digit can be identified by its coordinates (indices) in the two-dimensional representation space. The modification proposed in this paper, targeted to DSP inner product computations, uses a single digit representation for the coefficient vector and a 2-digit representation for the data vector. We show that a reduction of over 80% in hardware cost is possible using this hybrid representation compared to the original single-digit technique.

[1]  Graham A. Jullien,et al.  Theory and applications for a double-base number system , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

[2]  M. Ahmadi,et al.  Design of 1-D FIR filters with genetic algorithms , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[3]  Graham A. Jullien,et al.  Theory and Applications of the Double-Base Number System , 1999, IEEE Trans. Computers.

[4]  Majid Ahmadi,et al.  Design of 1-D FIR filters with genetic algorithms , 1999, ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications (IEEE Cat. No.99EX359).

[5]  E Swartzlander.  Digital optical arithmetic. , 1986, Applied optics.

[6]  A.A. Sawchuk,et al.  Digital optical computing , 1984, Proceedings of the IEEE.

[7]  Graham A. Jullien,et al.  Digital arithmetic using analog arrays , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[8]  David M. Lewis.  An accurate LNS arithmetic unit using interleaved memory function interpolator , 1993, Proceedings of IEEE 11th Symposium on Computer Arithmetic.

[9]  Graham A. Jullien,et al.  Designing FIR filters with enhanced Fermat ALUs , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).