Using PARBIT to Implement Partial Run-Time Reconfigurable Systems

Field Programmable Gate Arrays (FPGAs) can be used to implement partial run-time reconfigurable (RTR) systems. A tool called PARBIT has been developed that transforms FPGA configuration bitstreams into partial bitstreams. With this tool it is possible to define a partial reconfigurable area inside the FPGA and download it into a specified region of the FPGA device. This paper presents PARBIT, the methodology used to design the partial RTR system, and three application examples.

[1]  Brad L. Hutchings,et al.  Design methodologies for partially reconfigured systems , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[2]  Axel Jantsch,et al.  A Dynamically Reconfigurable FPGA-based Content Addressable Memory for IP Characterization , 2000 .

[3]  John W. Lockwood,et al.  Field programmable port extender (FPX) for distributed routing and queuing , 2000, FPGA '00.

[4]  Axel Jantsch,et al.  A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization , 2000, FPL.

[5]  Brad Hutchings,et al.  Designing a partially reconfigured system , 1995, Optics East.

[6]  Dzung T. Hoang,et al.  Searching genetic databases on Splash 2 , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[7]  P. Bertin,et al.  PAM programming environments: practice and experience , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[8]  Jonathan S. Turner,et al.  Design of a gigabit ATM switch , 1997, Proceedings of INFOCOM '97.

[9]  Martin Turner,et al.  An FPGA-based hardware accelerator for image processing , 1994 .

[10]  John W. Lockwood,et al.  Reprogrammable network packet processing on the field programmable port extender (FPX) , 2001, FPGA '01.

[11]  Scott McMillan,et al.  Partial Run-Time Reconfiguration Using JRTR , 2000, FPL.

[12]  John W. Lockwood,et al.  PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs) , 2001 .

[13]  Brad L. Hutchings,et al.  Implementation Approaches for Reconfigurable Logic Applications , 1995, FPL.