A new decoding scheme and erase sequence for 5 V only sector erasable flash memory

The authors describe a decoding scheme and erase sequence for a 5-V-only sector-erasable flash memory. A source line decoder eliminates the erase disturb problem and lowers the power consumption. The maximum switching voltage is reduced to 10 V, which makes possible a tight word line pitch for a 64-Mb flash memory. Narrow threshold voltage distribution of erased memory cells is obtained by programming after erase.<<ETX>>

[1]  Takeshi Okazawa,et al.  A 5V Only 16Mbit Flash EEPROM Cell Using Highly Reliable Write/Erase Technologies , 1991, 1991 Symposium on VLSI Technology.

[2]  Masamitsu Oshikiri,et al.  A self-convergence erasing scheme for a simple stacked gate flash EEPROM , 1991, International Electron Devices Meeting 1991 [Technical Digest].