A Versatile Clock Recovery Architecture and Monolithic Implementation

A family of monolithic phase-locked loops recover clock and retime NRZ data. At 155 MHz, random plus pattern jitter with a 27 code is 1.8 degrees rms, and static phase error is 4 degrees. Devices fabricated on both junction-isolated and dielectric-isolated bipolar processes are described. Measurement techniques to verify compliance with international telecommunication standards are also described.