G-vector: a new model for glitch analysis

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a general, but effective model for generation, propagation and elimination of glitches, enabling us to not only count the number of glitches but also locate the glitches so that such information can be utilized by system tools for the reduction of the number of glitches in the circuits. We provide a set of experimental results to demonstrate the effectiveness of our model.

[1]  Robert K. Brayton,et al.  Decomposition of logic functions for minimum transition activity , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[2]  Massoud Pedram,et al.  Power minimization in IC design: principles and applications , 1996, TODE.

[3]  Mary Jane Irwin,et al.  Accurate Estimation of Combinational Circuit Activity , 1995, 32nd Design Automation Conference.

[4]  Farid N. Najm,et al.  Transition density, a stochastic measure of activity in digital circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[5]  Kurt Keutzer,et al.  Estimation of average switching activity in combinational and sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.