Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits

Switched capacitors are commonly used in analog design. The circuit performance based on this technique relies on the accuracy of capacitance ratios, which are affected by random and systematic mismatches. To meet the accuracy requirement, designers can increase the layout area of unit capacitors to reduce random mismatch. Since increasing layout area enlarges the distance between unit capacitors, it induces more gradient errors, which results in larger systematic mismatch. Therefore, the better way for reducing the gradient errors is to carefully determine the locations of unit capacitors in a capacitor array. Moreover, the resulting placement must have high capacitance correlation in order to enhance yield. In this paper, we first explore the attributes of a good capacitor placement, which can reduce gradient errors and increase capacitance correlation. Then, an analytical-based approach is proposed to complete capacitor placement considering these issues. Finally, the results are optimized by arbitrarily swapping two unit capacitors. Compared with the simulated annealing based approach, the proposed method not only achieves better placement results but also gets 34x faster for the largest benchmark capacitor array.

[1]  Michel Steyaert,et al.  Influence of die attachment on MOS transistor matching , 1997 .

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  Measurement and modeling of MOS transistor current mismatch in analog IC's , 1994, ICCAD.

[3]  M. Vadipour,et al.  Gradient error cancellation and quadratic error reduction in unary and binary D/A converters , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[4]  A. Hastings.  The Art of Analog Layout , 2000 .

[5]  Mohamed Dessouky,et al.  Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Georges Gielen,et al.  A 14-bit intrinsic accuracy Q2 random walk CMOS DAC , 1999, IEEE J. Solid State Circuits.

[7]  Evangeline F. Y. Young,et al.  Analog placement with common centroid constraints , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[8]  Jai-Ming Lin,et al.  Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[9]  Ulf Schlichtmann,et al.  Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[10]  A. Maeda,et al.  A 10-bit 70 MS/s CMOS D/A converter , 1990 .

[11]  Chin-Long Wey,et al.  Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[13]  M. A. Copeland,et al.  Biquad alternatives for high-frequency switched-capacitor filters , 1985 .

[14]  Chin-Long Wey,et al.  Yield evaluation of analog placement with arbitrary capacitor ratio , 2009, 2009 10th International Symposium on Quality Electronic Design.

[15]  O. Nelles,et al.  An Introduction to Optimization , 1996, IEEE Antennas and Propagation Magazine.

[16]  Ko-Chi Kuo,et al.  A Switching Sequence for Linear Gradient Error Compensation in the DAC Design , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[17]  Antonio Petraglia,et al.  Automatic placement of identical unit capacitors to improve capacitance matching , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[18]  J. L. Dunkley,et al.  Systematic capacitance matching errors and corrective layout procedures , 1994 .

[19]  Chin-Long Wey,et al.  Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Stephan Henker,et al.  Modelling of capacitor mismatch and non-linearity effects ini charge redistribution SAR ADCs , 2010, Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2010.

[21]  Michel Steyaert,et al.  A 12-bit intrinsic accuracy high-speed CMOS DAC , 1998, IEEE J. Solid State Circuits.

[22]  Randall L. Geiger,et al.  Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays , 2000 .

[23]  Marcel J. M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[24]  Mohammed Ismail,et al.  Design techniques for improving intrinsic accuracy of resistor string DACs , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[25]  Evangeline F. Y. Young,et al.  Analog placement with common centroid and 1-D symmetry constraints , 2009, 2009 Asia and South Pacific Design Automation Conference.

[26]  Yao-Wen Chang,et al.  Thermal-driven analog placement considering device matching , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[27]  Gabor C. Temes,et al.  Random error effects in matched MOS capacitors and current sources , 1984 .