Tab with bumpless chips

Inner Lead Bonding is the starting process for people willing to enter into TAB technology; ILB has been almost always associated with gold bumps and the difficulties related to wafer bumping have for a long time acted as an argument against TAB. The increasing size of VLSI circuits has made more critical bump thickness control especially when ILB has to be performed by gang bonding (flatness and coplanarity errors have to be kept the same for a given bump thickness whatever the chip size). Several years ago, an alternate solution has appeared, called: single point ILB, this ILB process allows to treat independently each bond the same way as for wire bonding. Several wire bonder manufacturers are now offering efficient machines for performing ILB with that technique. When performing this process, each pad can be of an uneven thickness (the same way as for a complex hybrid) and in principle follow the same specification as for making wire bonding ( i.e. no bump). This development is described in the paper; it was started in 1979 in the EEC program Apachip and has been validated for internal products; the bumpless ILB can be applicable for most of the devices that are normally wire bonded, offering then the advantage of TAB without the drawback of pad bumping. Yields and reliability figures will be presented. They compare advantageously to bumped devices, and the field of application of that technology is that of the conventional TAB . Bumpless TAB can show specific advantage for very high density devices, where bump size represents a limitation; demonstration of ILB at 125, 100 and 75 gm pitch will be shown.