Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance

Many SoC architectures aimed at the multimedia domain support multiple use cases where only a subset of the applications is active at any time. Further, each multimedia application itself poses strict constraints on core-to-core communication latency. This paper presents an approach for automated synthesis of NoC architectures for such an SoC. We evaluated our design approach through comparisons with two existing techniques aimed at generating best effort and guaranteed throughput designs. Designs generated by our approach showed a marked improvement in both power consumption (12.3% decrease) and resource requirements (12.9% decrease) in comparison to the best effort NoC design approach. In comparison to the existing guaranteed throughput design approach our designs can guarantee core-to-core latency while consuming less power (8.1% decrease) and resources (7.9% decrease).

[1]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[2]  Radu Marculescu,et al.  Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures , 2003, DATE.

[3]  L. Benini,et al.  Designing Application-Specific Networks on Chips with Floorplan Information , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[4]  Sri Parameswaran,et al.  NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks , 2008, 2008 Asia and South Pacific Design Automation Conference.

[5]  Bill Lin,et al.  Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees , 2008, 2008 Asia and South Pacific Design Automation Conference.

[6]  Kees G. W. Goossens,et al.  A unified approach to constrained mapping and routing on network-on-chip architectures , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[7]  Radu Marculescu,et al.  Application-specific network-on-chip architecture customization via long-range link insertion , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[8]  Kees G. W. Goossens,et al.  Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[9]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[10]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[11]  Karam S. Chatha,et al.  Quality-of-service and error control techniques for mesh-based network-on-chip architectures , 2005, Integr..

[12]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[13]  Srinivasan Murali,et al.  A Methodology for Mapping Multiple Use-Cases onto Networks on Chips , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[14]  Ran Ginosar,et al.  QoS architecture and design process for cost effective Network on Chip , 2004 .

[15]  Jürgen Teich,et al.  CODES+ISSS 2007 , 2007 .

[16]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[17]  Radu Marculescu,et al.  Energy-aware mapping for tile-based NoC architectures under performance constraints , 2003, ASP-DAC '03.

[18]  Krishnan Srinivasan,et al.  Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms , 2007, 2007 Asia and South Pacific Design Automation Conference.

[19]  L. Benini,et al.  Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[20]  Glenn Leary,et al.  Performance and resource optimization of NoC router architecture for master and slave IP cores , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[21]  Alberto L. Sangiovanni-Vincentelli,et al.  Efficient synthesis of networks on chip , 2003, Proceedings 21st International Conference on Computer Design.

[22]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[23]  Axel Jantsch,et al.  Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[24]  Srinivasan Murali,et al.  Mapping and configuration methods for multi-use-case networks on chips , 2006, Asia and South Pacific Conference on Design Automation, 2006..