论文信息 - Chip-package codesign with redistribution layer

Chip-package codesign with redistribution layer

The use of redistribution layers to connect I/O circuit to the I/O pad is introduced and the electrical performance of a conceptual design with and without signal redistribution was compared.

Ananda Sarangi | Mahadevan Suryakumar | Yidnek Mekonnen

[1] James E. Jaussi,et al. A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[2] H. Heck,et al. Modeling and mitigating AC common mode conversion in multi-Gb/s differential printed circuit boards , 2004, Electrical Performance of Electronic Packaging - 2004.

[3] Zhonghua Wu,et al. Flip-chip redistribution layer electrical characterization and SSO noise simulation , 1997, Electrical Performance of Electronic Packaging.