A novel method in fractional synthesizers for a drastic decrease in lock time

A 1GHz frequency divider is presented in this paper. The proposed architecture aims to minimize lock time in Phase-Locked Loops (PLLs). Proposed structure has been simulated by HSPICE software in a typical 0.18μm CMOS technology at the supply voltage of 1.8V. Simulation results show that the designed divider locks in 2-20μs which is a lower lock time compared to conventional PLLs.

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