The DIBL effect of SOI p-channel FinFETs under various SDE lengths

Choosing a long source/drain extension length (LSDE) maybe effectively reduces the leakage between source/gate and drain/gate, but the S/D series resistance is increased and the drive current in p-channel FinFETs is suffered. Of course, the DIBL effect can be controlled well in device model and the channel punch-through effect also can be suppressed to decrease the standby current in ICs. Balancing the performance between OFF current and ON current is necessary. The DIBL and absolute VPT values at LSDE=160nm are superior to those at LSDE=60nm.