A capacitorless DRAM cell on SOI substrate

We propose a capacitorless DRAM (CDRAM) cell on SOI substrate with large READ current (>100 /spl mu/Aspl mu/m), small cell size, and simple fabrication process. PISCES simulations are used to analyze the memory cell operations. The CDRAM cell size is that of a transistor, which makes it very attractive for high density memory applications. Since the fabrication process of CDRAM is compatible with that of the general purpose SOI CMOS and complementary BiCMOS process, CDRAM can also be used for integrated on-chip memory and is an interesting candidate as the technology driver of SOI VLSI.<<ETX>>

[1]  N. Tanabe,et al.  A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell for 256 Mb DRAMs , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[2]  G.W. Taylor,et al.  A survey of high-density dynamic RAM cell concepts , 1979, IEEE Transactions on Electron Devices.

[3]  T. Kure,et al.  Super-low-voltage Operation Of A Semi-Static Complementary Gain DRAM Memory Cell , 1993, Symposium 1993 on VLSI Technology.

[4]  A. Nitayama,et al.  A Surrounding Gate Transistor (SGT) Gain Cell For Ultra High Density Drams , 1993, Symposium 1993 on VLSI Technology.

[5]  D. Erb.  Stratified charge memory , 1978, 1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  F. Horiguchi,et al.  A self-amplifying (SEA) cell for future high density DRAMs , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[7]  Chenming Hu,et al.  A versatile, SOI BiCMOS technology with complementary lateral BJT's , 1992, 1992 International Technical Digest on Electron Devices Meeting.