Mixed-VTH (MVT) CMOS circuit design for low power cell libraries
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[1] Kaushik Roy,et al. Low voltage low power CMOS design techniques for deep submicron ICs , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.
[2] Takayasu Sakurai,et al. Design methodology and optimization strategy for dual-VTH scheme using commercially available tools , 2001, ISLPED '01.
[3] Shin'ichiro Mutoh,et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.
[4] David Harris,et al. CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .
[5] Hiroshi Kawaguchi,et al. FP 12.4: A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current , 1998 .
[6] Kaushik Roy,et al. Mixed-Vth (MVT) CMOS circuit design methodology for low power applications , 1999, DAC '99.
[7] Dirk Timmermann,et al. Low power gate-level design with mixed-V/sub th/ (MVT) techniques , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).
[8] Satoshi Shigematsu,et al. A 1-V high-speed MTCMOS circuit scheme for power-down application circuits , 1997, IEEE J. Solid State Circuits.
[9] Kiat Seng Yeo,et al. Low Voltage, Low Power VLSI Subsystems , 2004 .
[10] Satoshi Shigematsu,et al. A 1-V high-speed MTCMOS circuit scheme for power-down applications , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..