Parametric yield management for 3D ICs: Models and strategies for improvement
暂无分享,去创建一个
[1] Emil Talpes,et al. Variability and energy awareness: a microarchitecture-level perspective , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[2] Arvind Kumar,et al. Three-dimensional integrated circuits , 2006, IBM J. Res. Dev..
[3] Rohit Kapur,et al. Speed binning with path delay test in 150-nm technology , 2003, IEEE Design & Test of Computers.
[4] M. Koyanagi,et al. New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration , 2006 .
[5] D CoryBruce,et al. Speed Binning with Path Delay Test in 150-nm Technology , 2003 .
[6] Bevan M. Baas,et al. A low-power, high-performance, 1024-point FFT processor , 1999, IEEE J. Solid State Circuits.
[7] Todd M. Austin,et al. The SimpleScalar tool set, version 2.0 , 1997, CARN.
[8] James D. Meindl,et al. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.
[9] James Tschanz,et al. Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[10] C. Morganti,et al. The asynchronous 24MB on-chip level-3 cache for a dual-core Itanium/sup /spl reg//-family processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[11] David Blaauw,et al. Modeling and analysis of parametric yield under power and performance constraints , 2005, IEEE Design & Test of Computers.
[12] Steven M. Nowick,et al. ACM Journal on Emerging Technologies in Computing Systems , 2010, TODE.
[13] Kevin Skadron,et al. Impact of Parameter Variations on Multi-Core Chips , 2006 .
[14] Martin Burtscher,et al. Bridging the processor-memory performance gap with 3D IC technology , 2005, IEEE Design & Test of Computers.
[15] J. Munkres. ALGORITHMS FOR THE ASSIGNMENT AND TRANSIORTATION tROBLEMS* , 1957 .
[16] Norman P. Jouppi,et al. CACTI: an enhanced cache access and cycle time model , 1996, IEEE J. Solid State Circuits.
[17] Anantha Chandrakasan,et al. Timing, energy, and thermal performance of three-dimensional integrated circuits , 2004, GLSVLSI '04.
[18] Ulrich Ramacher,et al. 3D chip stack technology using through-chip interconnects , 2005, IEEE Design & Test of Computers.
[19] C.H. Kim,et al. PVT-aware leakage reduction for on-die caches with improved read stability , 2005, IEEE Journal of Solid-State Circuits.
[20] Mahmut T. Kandemir,et al. Design and Management of 3D Chip Multiprocessors Using Network-in-Memory , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).
[21] Robert S. Patti,et al. Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.
[22] RedaSherief,et al. Parametric yield management for 3D ICs , 2008 .
[23] Robert S. Patti. Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs In 3D integrated circuits, analog, digital, flash and DRAM wafers are processed separately, then brought together in an integrated vertical stack. , 2006 .
[24] M. Koyanagi,et al. New three-dimensional integration technology to achieve a super chip , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.
[25] Kurt Keutzer,et al. Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[26] E. Beyne. 3D interconnection and packaging: impending reality or still a dream? , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[27] Narayanan Vijaykrishnan,et al. Three-dimensional cache design exploration using 3DCacti , 2005, 2005 International Conference on Computer Design.
[28] Noel Menezes,et al. Repeater scaling and its impact on CAD , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[29] Ke Meng,et al. Process Variation Aware Cache Leakage Management , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.
[30] Jian Xu,et al. Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.
[31] Aamir Zia,et al. Predicting the performance of a 3D processor-memory chip stack , 2005, IEEE Design & Test of Computers.
[32] J. Baliga. Chips go vertical [3D IC interconnection] , 2004, IEEE Spectrum.
[33] Wim Dehaene,et al. Statistically aware SRAM memory array design , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[34] James D. Meindl. Interconnect limits on gigascale integration (GSI) , 2001, 2001 6th International Symposium on Plasma- and Process-Induced Damage (IEEE Cat. No.01TH8538).
[35] Kaustav Banerjee,et al. A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[36] David S. Johnson,et al. Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .
[37] Kaustav Banerjee,et al. Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.
[38] H. Kuhn. The Hungarian method for the assignment problem , 1955 .
[39] Yuan Xie,et al. Design space exploration for 3D architectures , 2006, JETC.
[40] Kenneth Rose,et al. First-order performance prediction of cache memory with wafer-level 3D integration , 2005, IEEE Design & Test of Computers.
[41] Yu Cao,et al. Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[42] C.K. Chen,et al. A wafer-scale 3-D circuit integration technology , 2006, IEEE Transactions on Electron Devices.
[43] William J. Cook,et al. Computing Minimum-Weight Perfect Matchings , 1999, INFORMS J. Comput..
[44] J.D. Meindl,et al. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[45] Wei Zhao. Predictive technology modeling for scaled CMOS , 2009 .
[46] Kaushik Roy,et al. Speed binning aware design methodology to improve profit under parameter variations , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[47] Sarma B. K. Vrudhula,et al. A methodology to improve timing yield in the presence of process variations , 2004, Proceedings. 41st Design Automation Conference, 2004..
[48] Kaustav Banerjee,et al. Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[49] Kaustav Banerjee,et al. 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.
[50] G. Smith,et al. Yield considerations in the choice of 3D technology , 2007, 2007 International Symposium on Semiconductor Manufacturing.
[51] S. Das,et al. Fabrication technologies for three-dimensional integrated circuits , 2002, Proceedings International Symposium on Quality Electronic Design.