Networks on Chip: The New Trend of On-Chip Interconnection

With continuous shrinking in the size of deep sub-micron in this million transistor era, the interconnection of these hundreds and thousands of cores on a single chip is still constraint. Providing an efficient communication among these cores is a major challenge in the on-chip domain. Although hierarchical architecture has addressed most of the issues of the traditional approaches like point-to-point and bus architecture, scalability still remains to be a limitation. Network on chip architecture provides a viable solution to all these issues. A network is established on the chip among the cores and communication occurs through this network, making it highly efficient and mostly scalable. In this paper we present a brief introduction to network-on-chip along with some of its popular topologies and routing techniques. Also, some of the major challenges of network-on-chip have been stated.