Three-phase short-circuit fault implementation in converter based transmission line emulator

A hardware test-bed (HTB) has been developed to realize power system emulation by mimicking the system components with universal three-phase voltage source converters (VSCs). The VSC-based transmission line emulator has also been successfully developed to flexibly represent interconnected ac lines under normal operating conditions. As the most serious short-circuit fault condition, the three-phase short-circuit fault emulation is essential for power system studies. This paper proposes a model to realize the three-phase short-circuit fault emulation within the emulated transmission line. At the same time, a combination method is proposed to eliminate the undesired transients caused by the current reference step changes while switching between the fault state and normal state.

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