Overview and outlook of through‐silicon via (TSV) and 3D integrations

Purpose – The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.Design/methodology/approach – This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.Findings – A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3...

[1]  Yee-Wen Yen,et al.  Interfacial Reactions in Sn/Fe-xNi Couples , 2011, Journal of Electronic Materials.

[2]  Michael S. Shur,et al.  Bandgap engineering in MBE grown Al1−xGaxN epitaxial columnar nanostructures , 2012 .

[3]  J. Lau,et al.  A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications , 2008, 2008 58th Electronic Components and Technology Conference.

[4]  N. Kernevez,et al.  Three dimensional chip stacking using a wafer-to-wafer integration , 2007, 2007 IEEE International Interconnect Technology Conferencee.

[5]  X. Gu,et al.  A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding , 2008, 2008 IEEE International Electron Devices Meeting.

[6]  T. Nishimura,et al.  Concept and basic technologies for 3-D IC structure , 1986, 1986 International Electron Devices Meeting.

[7]  D. Pinjala,et al.  Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages , 2009, IEEE Transactions on Components and Packaging Technologies.

[8]  Paul S. Andry,et al.  Fabrication and characterization of robust through-silicon vias for silicon-carrier applications , 2008, IBM J. Res. Dev..

[9]  Tadatomo Suga,et al.  A novel moiré fringe assisted method for nanoprecision alignment in wafer bonding , 2009, Electronic Components and Technology Conference.

[10]  John H. Lau,et al.  Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking , 2009, 2009 59th Electronic Components and Technology Conference.

[11]  John H. Lau,et al.  Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package , 2009, 2009 59th Electronic Components and Technology Conference.

[12]  John H. Lau,et al.  Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects , 2009, 2009 59th Electronic Components and Technology Conference.

[13]  Anna W. Topol,et al.  Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits , 2006, 2006 International Electron Devices Meeting.

[14]  Siow Pin Tan,et al.  Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules , 2010, IEEE Transactions on Components and Packaging Technologies.

[15]  John H. Lau,et al.  Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps , 2009, 2009 59th Electronic Components and Technology Conference.

[16]  John Hon-Shing Lau,et al.  Design and process of 3D MEMS packaging , 2009 .

[17]  John H. Lau,et al.  Effect of TSV interposer on the thermal performance of FCBGA package , 2009, 2009 11th Electronics Packaging Technology Conference.

[18]  Chen Shan,et al.  Statistical key variable analysis and model-based control for improvement performance in a deep reactive ion etching process , 2012 .

[19]  C. K. Chen,et al.  Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers , 2009, 2009 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[20]  A. Kumar,et al.  Effect of wafer back grinding on the mechanical behavior of multilayered low-k for 3D-stack packaging applications , 2008, 2008 58th Electronic Components and Technology Conference.

[21]  T. Suga,et al.  Au–Au Surface-Activated Bonding and Its Application to Optical Microsensors With 3-D Structure , 2009, IEEE Journal of Selected Topics in Quantum Electronics.

[22]  R. Beica,et al.  Through silicon via copper electrodeposition for 3D integration , 2008, Electronic Components and Technology Conference.

[23]  J.M. Knecht,et al.  Effects of Through-BOX Vias on SOI MOSFETs , 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

[24]  Xiaowu Zhang,et al.  Development of 3-D Silicon Module With TSV for System in Packaging , 2010, IEEE Transactions on Components and Packaging Technologies.

[25]  J.M. Knecht,et al.  Thermal Effects of Three Dimensional Integrated Circuit Stacks , 2007, 2007 IEEE International SOI Conference.

[26]  Tadatomo Suga,et al.  Moiré method for nanoprecision wafer-to-wafer alignment: Theory, simulation and application , 2009, 2009 International Conference on Electronic Packaging Technology & High Density Packaging.

[27]  N. Kernevez,et al.  Challenges for 3D IC integration: bonding quality and thermal management , 2007, 2007 IEEE International Interconnect Technology Conferencee.

[28]  C.K. Chen,et al.  A wafer-scale 3-D circuit integration technology , 2006, IEEE Transactions on Electron Devices.

[29]  Qing Xin Zhang,et al.  Application of piezoresistive stress sensors in ultra thin device handling and characterization , 2009 .

[30]  John H. Lau.  State-of-the-art and trends in 3D IC/Si integrations and WLP , 2010, 2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT).

[31]  J. Lau,et al.  Thermal management of 3D IC integration with TSV (through silicon via) , 2009, 2009 59th Electronic Components and Technology Conference.

[32]  C. Y. Khor,et al.  Analysis of encapsulation process in 3D stacked chips with different microbump array , 2012 .

[33]  Peter Ramm,et al.  3D Integration: Technology and Applications , 2008 .

[34]  K. Takahashi,et al.  Through Silicon Via and 3-D Wafer/Chip Stacking Technology , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[35]  V. Lee,et al.  Development of 3D silicon module with TSV for system in packaging , 2008, 2008 58th Electronic Components and Technology Conference.

[36]  John H. Lau,et al.  Fabrication of silicon carriers with TSV electrical interconnections and embedded thermal solutions for high power 3-D package , 2008, ECTC 2008.

[37]  H. Reichl,et al.  Through silicon via technology — processes and reliability for wafer-level 3D system integration , 2008, 2008 58th Electronic Components and Technology Conference.

[38]  A. Shigetou,et al.  Bumpless Interconnect of 6- $\mu$m-Pitch Cu Electrodes at Room Temperature , 2008, IEEE Transactions on Advanced Packaging.

[39]  P. Healey,et al.  Three-dimensional integration of silicon-on-insulator RF amplifier , 2008 .

[40]  T. Itoh,et al.  Bumpless interconnect through ultrafine Cu electrodes by means of surface-activated bonding (SAB) method , 2006, IEEE Transactions on Advanced Packaging.

[41]  John H. Lau,et al.  3D packaging with through ilicon via (TSV) for electrical and fluidic interconnections , 2009, 2009 59th Electronic Components and Technology Conference.

[42]  M. Matsuo,et al.  Novel low cost integration of through chip interconnection and application to CMOS image sensor , 2006, 56th Electronic Components and Technology Conference 2006.

[43]  J.M. Knecht,et al.  Scaling Three-Dimensional SOI Integrated-Circuit Technology , 2007, 2007 IEEE International SOI Conference.

[44]  Sung Kyu Lim,et al.  Effective thermal via and decoupling capacitor insertion for 3D system-on-package , 2006, 56th Electronic Components and Technology Conference 2006.

[45]  Y.-L. Shen,et al.  Misalignment induced shear deformation in 3D chip stacking: A parametric numerical assessment , 2013, Microelectron. Reliab..

[46]  K.-N. Chen,et al.  Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding , 2006, 2009 Symposium on VLSI Technology.

[47]  James F. Gibbons,et al.  cw laser anneal of polycrystalline silicon: Crystalline structure, electrical properties , 1978 .

[48]  John H. Lau,et al.  Effects of TSVs (through-silicon vias) on thermal performances of 3D IC integration system-in-package (SiP) , 2012, Microelectron. Reliab..

[49]  Y.-L. Shen,et al.  Thermal expansion behavior of through-silicon-via structures in three-dimensional microelectronic packaging , 2012, Microelectron. Reliab..

[50]  Y. Akasaka.  Three-dimensional IC trends , 1986, Proceedings of the IEEE.

[51]  John H. Lau,et al.  TSV manufacturing yield and hidden costs for 3D IC integration , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[52]  M.T.W. de Langen.  Low Cost Flip Chip Technology , 1997 .

[53]  Jun Wang,et al.  Thermal analysis and heat dissipation optimization of 3D packaging with TSV interposer , 2012 .

[54]  B. Dang,et al.  3D silicon integration , 2008, 2008 58th Electronic Components and Technology Conference.

[55]  J. Lau,et al.  C2W bonding method for MEMS applications , 2008, 2008 10th Electronics Packaging Technology Conference.

[56]  T. Kurihara,et al.  A Silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect , 2008, 2008 58th Electronic Components and Technology Conference.

[57]  C. Selvanayagam,et al.  Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps , 2009, IEEE Transactions on Advanced Packaging.

[58]  T. Kurihara,et al.  Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring , 2008, 2008 58th Electronic Components and Technology Conference.

[59]  D. Kwong,et al.  Study of 15µm pitch solder microbumps for 3D IC integration , 2009, 2009 59th Electronic Components and Technology Conference.

[60]  Maud Vinet,et al.  System on Wafer: A New Silicon Concept in SiP , 2009, Proceedings of the IEEE.

[61]  Yutaka Tsukada.  Flip chip technology , 2010, 2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT).

[62]  H. Reichl,et al.  High aspect ratio TSV copper filling with different seed layers , 2008, 2008 58th Electronic Components and Technology Conference.

[63]  X. Baillin,et al.  Through silicon vias technology for CMOS image sensors packaging , 2008, 2008 58th Electronic Components and Technology Conference.

[64]  John H. Lau,et al.  3D LED and IC wafer level packaging , 2010 .

[65]  A. Kumar,et al.  Development of Fine Pitch Solder Microbumps for 3D Chip Stacking , 2008, 2008 10th Electronics Packaging Technology Conference.

[66]  Nobuo Hayasaka,et al.  Silicon interposer technology for high-density package , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[67]  Heeseok Lee,et al.  Power Delivery Network Design for 3D SIP Integrated over Silicon Interposer Platform , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

[68]  Vyshnavi Suntharalingam,et al.  Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.