Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs

Abstract Interposer-based 2.5-dimensional integrated circuit (2.5D IC) is considered as a promising solution to problems like wire delay and power consumption faced by the semiconductor industry today. Since the interconnect wires in the silicon interposer may be defective during fabrication and assembly, they must be adequately tested to ensure product qualification. This paper presents an efficient interconnect test architecture to detect open, short and delay faults, which is compatible with the IEEE 1149.1 standard. It provides a new boundary scan structure with low test power consumption. To reduce the overall test cost, a data-package based test structure is proposed to match the test data transfer volume between TSVs and scan chains. Interconnects of multiple dies can be tested simultaneously under constrains of test power with minimum external test pins. The simulation results validate the effectiveness of the proposed test method. We also present synthesis results to evaluate the area overhead.

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