On the complexity of universal fault diagnosis for look-up table FPGAs
暂无分享,去创建一个
[1] Yervant Zorian,et al. Test of RAM-based FPGA: methodology and application to the interconnect , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[2] Hideo Fujiwara,et al. A test methodology for interconnect structures of LUT-based FPGAs , 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).
[3] Fabrizio Lombardi,et al. An approach for testing programmable/configurable field programmable gate arrays , 1996, Proceedings of 14th VLSI Test Symposium.
[4] Michael Hermann,et al. Fault Modeling and Test Generation for FPGAs , 1994, FPL.
[5] Hideo Fujiwara,et al. Universal test complexity of field-programmable gate arrays , 1995, Proceedings of the Fourth Asian Test Symposium.
[6] 丸山 勉,et al. Field Programmable Gate Array による複雑適応系の計算の高速化 , 1999 .
[7] Michael Nicolaidis,et al. A Test Methodology Applied to Cellular Logic Programmable Gate Arrays , 1994, FPL.
[8] Fabrizio Lombardi,et al. Diagnosing Programmable Interconnect Systems for FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.
[9] Arthur D. Friedman,et al. Easily Testable Iterative Systems , 1973, IEEE Transactions on Computers.
[10] Fabrizio Lombardi,et al. On the diagnosis of programmable interconnect systems: Theory and application , 1996, Proceedings of 14th VLSI Test Symposium.