GF(24) multiplier in hardware using discrete neural network
暂无分享,去创建一个
Francisco Marcos de Assis | Raimundo Carlos Silvério Freire | Vanderson Lima Reis | Wendell E. M. Costa | Ewaldo Eder Santana | R. Freire | F. M. Assis | V. L. Reis | Ewaldo E. C. Santana
[1] Yusuf Leblebici,et al. A compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gates , 1996 .
[2] Chiou-Yng Lee,et al. Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials , 2001, IEEE Trans. Computers.
[3] J. C. Tejero,et al. A threshold logic gate based on clocked coupled inverters , 1998 .
[4] Derek Abbott,et al. Threshold logic parallel counters for 32-bit multipliers , 2002, SPIE Micro + Nano Materials, Devices, and Applications.
[5] Christof Paar,et al. A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields , 1996, IEEE Trans. Computers.
[6] Trieu-Kien Truong,et al. Systolic Multipliers for Finite Fields GF(2m) , 1984, IEEE Transactions on Computers.
[7] Toshiya Itoh,et al. Structure of Parallel Multipliers for a Class of Fields GF(2^m) , 1989, Inf. Comput..