A scan BIST generation method using a markov source and partial bit-fixing

Recently, Markov sources were shown to be effective in designing pseudo-random test pattern generators with low area overhead for built-in self-test of scan designs. This paper presents a new test pattern generation scheme based on a Markov source and a partial bit-fixing technique. A new method is proposed for the computation of the state transition probabilities of the Markov source based on the statistics of a deterministic test set. This is enhanced by partial bit-fixing logic, which fixes a group of consecutive inputs to all-0 or all-1. Experimental results show that the proposed BIST scheme can achieve 100% fault coverage for large benchmark circuits with reduced hardware overhead and reduced pattern counts compared to the earlier method using Markov sources.

[1]  S. Hellebrand,et al.  An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[2]  Bernard Courtois,et al.  Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers , 1992 .

[3]  Nur A. Touba,et al.  Virtual scan chains: a means for reducing scan length in cores , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[4]  Irith Pomeranz,et al.  Pseudo random patterns using Markov sources for scan BIST , 2002, Proceedings. International Test Conference.

[5]  Gundolf Kiefer,et al.  Deterministic BIST with multiple scan chains , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[6]  Irith Pomeranz,et al.  3-weight Pseudo-random Test Generation Based on a Deterministic Test Set for Combinational and Sequential Circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[8]  Gundolf Kiefer,et al.  Bit-flipping BIST , 1996, Proceedings of International Conference on Computer Aided Design.

[9]  Seongrnoon Wang,et al.  Low hardware overhead scan based 3-weight weighted random BIST , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[10]  Nur A. Touba,et al.  Bit-fixing in pseudorandom sequences for scan BIST , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Janusz Rajski,et al.  Constructive multi-phase test point insertion for scan-based BIST , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[12]  Benoit Nadeau-Dostie,et al.  A new procedure for weighted random built-in self-test , 1990, Proceedings. International Test Conference 1990.

[13]  B. Koneman,et al.  LFSR-Coded Test Patterns for Scan Designs , 1993 .

[14]  Hans-Joachim Wunderlich,et al.  Multiple distributions for biased random test patterns , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.