HotSpot minimization using fine-grained DVS architecture at 90 nm technology

Power and temperature has become the major design challenges in the development of today's complex low power digital integrated circuits due to the adverse effect of these parameters on performance, reliability, cooling and packing costs, as well as increase in leakage power as we gradually move towards deep submicron technology. The increasing adoption of fine-grained power management strategies in design synthesis flow has motivated us to build power and temperature conscious designs using such strategies at the behavioral level. In this paper, we propose power and temperature aware multi-objective scheduling and binding algorithms during behavioral synthesis stage using fine-grained dynamic voltage scaling enabled functional units to alleviate the problem of localized heating, which often leads to hotspot zones in chips.

[1]  Majid Sarrafzadeh,et al.  Scheduling with multiple voltages , 1997, Integr..

[2]  Li Shang,et al.  TAPHS: thermal-aware unified physical-level and high-level synthesis , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[3]  Seda Ogrenci Memik,et al.  An Integrated Approach to Thermal Management in High-Level Synthesis , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Benton H. Calhoun,et al.  Power switch characterization for fine-grained dynamic voltage scaling , 2008, 2008 IEEE International Conference on Computer Design.

[5]  Taewhan Kim,et al.  Thermal-Aware High-Level Synthesis Based on Network Flow Method , 2009, J. Circuits Syst. Comput..

[6]  Tughrul Arslan,et al.  Multi-objective design strategy for high-level low power design of DSP systems , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[7]  Yu-Chin Hsu,et al.  A formal approach to the scheduling problem in high level synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Pallab Dasgupta,et al.  Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture , 2012, ACITY.

[9]  Pallab Dasgupta,et al.  Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework , 2012, 2012 International Symposium on Electronic System Design (ISED).

[10]  Benton H. Calhoun,et al.  Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design , 2009, 2009 IEEE International Conference on Computer Design.

[11]  Massoud Pedram,et al.  Register Allocation and Binding for Low Power , 1995, 32nd Design Automation Conference.

[12]  Reinaldo A. Bergamaschi,et al.  Scheduling under resource constraints and module assignment , 1991, Integr..

[13]  Raul Camposano,et al.  Path-based scheduling for synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Qiang Zhou,et al.  Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources , 2009, 2009 Asia and South Pacific Design Automation Conference.

[15]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..