Top-Down Technology for Reconfigurable Nanowire FETs With Symmetric On-Currents

In this paper, a technology for top-down single-gated Schottky barrier transistor is presented exhibiting the highest symmetry of on-currents for n- and p-conductance of such silicon-on-insulator-based devices. The symmetry in the current-voltage-characteristics is a mandatory requirement to realize circuits with reconfigurable nanowire field effect transistors (RFETs) whose channel can be switched electrostatically between n- and p-conductance. It was achieved by an oxidation-induced stressor layer covering the nanowire. Together with the demand for only a single gate potential level, this opens the route to build top-down RFET circuits. Our device features an atomically sharp Schottky junction between intruded nickel silicide and the intrinsic nanowire channel.

[1]  G. De Micheli,et al.  Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs , 2012, 2012 International Electron Devices Meeting.

[2]  Michael T. Niemier,et al.  Using emerging technologies for hardware security beyond PUFs , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[3]  Marcus Völp,et al.  Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  Stefan Slesazeck,et al.  Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors , 2015, IEEE Transactions on Nanotechnology.

[5]  Giovanni De Micheli,et al.  Advanced system on a chip design based on controllable-polarity FETs , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[6]  Walter Riess,et al.  Donor deactivation in silicon nanostructures. , 2009, Nature nanotechnology.

[7]  Thomas Mikolajick,et al.  Tuning the tunneling probability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors , 2017 .

[8]  G. Cunge,et al.  HSQ hybrid lithography for 20 nm CMOS devices development , 2002 .

[9]  G. De Micheli,et al.  Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages , 2014, IEEE Transactions on Electron Devices.

[10]  Pascal Gentile,et al.  Multifunctional devices and logic gates with undoped silicon nanowires. , 2012, Nano letters.

[11]  Thomas Mikolajick,et al.  Dually active silicon nanowire transistors and circuits with equal electron and hole transport. , 2013, Nano letters.

[12]  Masahiro Asada,et al.  Analysis of Short-Channel Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistor on Silicon-on-Insulator Substrate and Demonstration of Sub-50-nm n-type Devices with Metal Gate , 1999 .

[13]  Falco C. M. J. M. van Delft,et al.  Hydrogen silsesquioxane/novolak bilayer resist for high aspect ratio nanoscale electron-beam lithography , 2000 .

[14]  Thomas Mikolajick,et al.  Reconfigurable Nanowire Electronics-Enabling a Single CMOS Circuit Technology , 2014, IEEE Transactions on Nanotechnology.

[15]  Thomas Mikolajick,et al.  Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions. , 2017, ACS nano.

[16]  Giovanni De Micheli,et al.  A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Stefan Slesazeck,et al.  Elementary Aspects for Circuit Implementation of Reconfigurable Nanowire Transistors , 2014, IEEE Electron Device Letters.

[18]  Akash Kumar,et al.  Exploiting transistor-level reconfiguration to optimize combinational circuits , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[19]  Thomas Mikolajick,et al.  Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors , 2017, Reports on progress in physics. Physical Society.

[20]  G. De Micheli,et al.  A Schottky-barrier silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 decades of current , 2014, 2014 IEEE International Electron Devices Meeting.

[21]  Thomas Mikolajick,et al.  Strain-engineering for improved tunneling in reconfigurable silicon nanowire transistors , 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

[22]  Roger Fabian W. Pease,et al.  Self‐limiting oxidation of Si nanowires , 1993 .

[23]  U. Schwalke,et al.  Dopant-independent and voltage-selectable silicon-nanowire-CMOS technology for reconfigurable logic applications , 2010, 2010 Proceedings of the European Solid State Device Research Conference.

[24]  G. De Micheli,et al.  Ambipolar Gate-Controllable SiNW FETs for Configurable Logic Circuits With Improved Expressive Capability , 2012, IEEE Electron Device Letters.

[25]  Thomas Mikolajick,et al.  Parallel arrays of Schottky barrier nanowire field effect transistors: Nanoscopic effects for macroscopic current output , 2013, Nano Research.

[26]  Udo Schwalke,et al.  CMOS without doping: Multi-gate silicon-nanowire field-effect-transistors , 2012 .

[27]  S. Thoms,et al.  Comparison of hydrogen silsesquioxane development methods for sub-10 nm electron beam lithography using accurate linewidth inspection , 2011 .

[28]  P. Lugli,et al.  Non-Linear Gate Length Dependence of On-Current in Si-Nanowire FETs , 2006, 2006 European Solid-State Device Research Conference.

[29]  Yasuo Takahashi,et al.  Three-dimensional siloxane resist for the formation of nanopatterns with minimum linewidth fluctuations , 1998 .

[30]  Stefan Slesazeck,et al.  Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits , 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

[31]  Wei Lu,et al.  Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures , 2004 .

[32]  Thomas Mikolajick,et al.  Reconfigurable nanowire electronics – A review , 2014 .

[33]  J. Fluitman,et al.  A survey on the reactive ion etching of silicon in microtechnology , 1996 .

[34]  Stefan Slesazeck,et al.  Reconfigurable silicon nanowire transistors. , 2012, Nano letters.

[35]  Yusuf Leblebici,et al.  Vertically-stacked double-gate nanowire FETs with controllable polarity: From devices to regular ASICs , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[36]  Udo Schwalke,et al.  Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications , 2015 .

[37]  Min Zhang,et al.  On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs , 2006, IEEE Transactions on Electron Devices.

[38]  M. Lenzlinger,et al.  Fowler‐Nordheim Tunneling into Thermally Grown SiO2 , 1969 .

[39]  Thomas Mikolajick,et al.  Silicon nanowires – a versatile technology platform , 2013 .

[40]  James L Erskine,et al.  Diffusion layers and the Schottky-barrier height in nickel silicide-silicon interfaces , 1983 .

[41]  E. Vogel,et al.  Enhanced channel modulation in dual-gated silicon nanowire transistors. , 2005, Nano letters.

[42]  Charles M. Lieber,et al.  Diameter-controlled synthesis of single-crystal silicon nanowires , 2001 .

[43]  Thomas Mikolajick,et al.  Printable Parallel Arrays of Si Nanowire Schottky-Barrier-FETs With Tunable Polarity for Complementary Logic , 2016, IEEE Transactions on Nanotechnology.

[44]  Mark Y. Liu,et al.  A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size , 2014, 2014 IEEE International Electron Devices Meeting.

[45]  Yusuf Leblebici,et al.  Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity , 2014, IEEE Transactions on Nanotechnology.

[46]  Paolo Lugli,et al.  Silicon nanowires: catalytic growth and electrical characterization , 2006 .

[47]  N. Loubet,et al.  Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length , 2012, IEEE Electron Device Letters.

[48]  Abbes Tahraoui,et al.  Top-gated silicon nanowire transistors in a single fabrication step. , 2009, ACS nano.

[49]  Thomas Mikolajick,et al.  Stress-Dependent Performance Optimization of Reconfigurable Silicon Nanowire Transistors , 2015, IEEE Electron Device Letters.

[50]  Luca Gaetano Amarù,et al.  Nanowire systems: technology and design , 2014, Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences.