EAST: Efficient Assertion Simulation techniques

In the context of simulation-based verification, the Assertion-based Verification (ABV) methodology has become the technology of choice, with increasing proliferation of Verification / Assertion IPs for most commonly used protocols. To support the ABV flow, current generation simulators typically create threads for the assertions and evaluate each assertion separately by converting them into finite state automatons and monitoring their states during simulation. In this paper, we propose a different technique for assertion evaluation in a simulation-based verification flow. The proposed technique, EAST (Efficient Assertion Simulation Techniques), handles assertions in groups, instead of examining them in isolation, and achieves significant performance benefits. To this effect, our algorithm has a preprocessing phase (prior to simulation) which creates a shared data structure from the set of assertions using some simple rules, based on the assertion language operators. This is attached with the simulator and during simulation, at each evaluation cycle, EAST infers the decision of the assertions by a combination of lookup and substitution. We present our proposal using Linear Temporal Logic (LTL) assertions in this paper. Our prototype, EAST, achieves promising performance numbers in terms of both runtime and peak memory for both random and standard benchmark protocol designs.

[1]  Moshe Y. Vardi,et al.  Optimized temporal monitors for SystemC , 2012, Formal Methods Syst. Des..

[2]  Koji Ara,et al.  A proposal for transaction-level verification with Component Wrapper Language , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[3]  Raimund Ubar,et al.  PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams , 2009, J. Electron. Test..

[4]  Moshe Y. Vardi,et al.  Deterministic Dynamic Monitors for Linear-Time Assertions , 2006, FATES/RV.

[5]  Avner Landver,et al.  The ForSpec Temporal Logic: A New Temporal Property-Specification Language , 2002, TACAS.

[6]  William P. Birmingham,et al.  A symbolic-simulation approach to the timing verification of interacting FSMs , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[7]  Yi-Jong Yeh,et al.  A simulation-based temporal assertion checker for PSL , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[8]  Amir Pnueli,et al.  The temporal logic of programs , 1977, 18th Annual Symposium on Foundations of Computer Science (sfcs 1977).

[9]  István Majzik,et al.  Automatic generation of executable assertions for runtime checking temporal requirements , 2005, Ninth IEEE International Symposium on High-Assurance Systems Engineering (HASE'05).