EAST: Efficient Assertion Simulation techniques
暂无分享,去创建一个
[1] Moshe Y. Vardi,et al. Optimized temporal monitors for SystemC , 2012, Formal Methods Syst. Des..
[2] Koji Ara,et al. A proposal for transaction-level verification with Component Wrapper Language , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[3] Raimund Ubar,et al. PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams , 2009, J. Electron. Test..
[4] Moshe Y. Vardi,et al. Deterministic Dynamic Monitors for Linear-Time Assertions , 2006, FATES/RV.
[5] Avner Landver,et al. The ForSpec Temporal Logic: A New Temporal Property-Specification Language , 2002, TACAS.
[6] William P. Birmingham,et al. A symbolic-simulation approach to the timing verification of interacting FSMs , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.
[7] Yi-Jong Yeh,et al. A simulation-based temporal assertion checker for PSL , 2003, 2003 46th Midwest Symposium on Circuits and Systems.
[8] Amir Pnueli,et al. The temporal logic of programs , 1977, 18th Annual Symposium on Foundations of Computer Science (sfcs 1977).
[9] István Majzik,et al. Automatic generation of executable assertions for runtime checking temporal requirements , 2005, Ninth IEEE International Symposium on High-Assurance Systems Engineering (HASE'05).