Low-on-resistance strain-controlled LDMOS transistors for 0.25-μm power ICs
暂无分享,去创建一个
[1] Y. Hoshino,et al. Strained-silicon MOSFETs for analog applications: utilizing a supercritical-thickness strained Layer for low leakage current and high breakdown Voltage , 2006, IEEE Transactions on Electron Devices.
[2] J. Welser,et al. Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors , 1994, IEEE Electron Device Letters.
[3] I. De Wolf,et al. Stress-Induced Mobility Enhancement for Integrated Power Transistors , 2007, 2007 IEEE International Electron Devices Meeting.
[4] I. De Wolf,et al. Theoretical and experimental Raman spectroscopy study of mechanical stress induced by electronic packaging , 2005 .
[5] Satoshi Tanaka,et al. Measurement of in-plane and depth strain profiles in strained-Si substrates , 2007 .
[6] Kevin Barraclough,et al. I and i , 2001, BMJ : British Medical Journal.
[7] T. Ando,et al. A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applications , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[8] Kozo Sakamoto,et al. Low on-resistance and low feedback-charge, lateral power MOSFETs with multi-drain regions for high-efficient DC/DC converters , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.
[9] W. Marsden. I and J , 2012 .
[10] P. Besser,et al. Band offset induced threshold variation in strained-Si nMOSFETs , 2003, IEEE Electron Device Letters.
[11] J. Fossum,et al. On the threshold Voltage of strained-Si-Si/sub 1-x/Ge/sub x/ MOSFETs , 2005, IEEE Transactions on Electron Devices.
[12] H. Nayfeh,et al. A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs , 2004, IEEE Transactions on Electron Devices.
[13] Yoshida Isao,et al. A highly efficient 1.9-GHz Si high-power MOS amplifier , 1998 .