GTL IO standards based WLAN specific low power ALU design on FPGA
暂无分享,去创建一个
[1] J. Yadav,et al. Energy efficient design and implementation of ALU on 40nm FPGA , 2013, 2013 International Conference on Energy Efficient Technologies for Sustainability.
[2] M. Pattanaik,et al. Clock gating based energy efficient ALU design and implementation on FPGA , 2013, 2013 International Conference on Energy Efficient Technologies for Sustainability.
[3] Sudhir Rao Rupanagudi,et al. Area and Speed Efficient Arithmetic Logic Unit Design Using Ancient Vedic Mathematics on FPGA , 2013 .
[4] Bishwajeet Pandey,et al. Clock Gating Aware Low Power ALU Design and Implementation on FPGA , 2013 .
[5] Tanesh Kumar,et al. LVDCI I/O standard based green image ALU design on ultra scale FPGA , 2013, 2013 IEEE 8th International Conference on Industrial and Information Systems.
[6] Vinay Kumar Singh,et al. VHDL Environment for Floating Point Arithmetic Logic Unit-ALU Design and Simulation , 2011, 2011 International Conference on Communication Systems and Network Technologies.
[7] Manisha Pattanaik,et al. Drive Strength and LVCMOS Based Dynamic Power Reduction of ALU on FPGA , 2013 .
[8] Bishwajeet Pandey,et al. IO standard based energy efficient ALU design and implementation on 28nm FPGA , 2013, 2013 Annual IEEE India Conference (INDICON).