Trends Toward Low-Voltage Power Supplies

Two factors, technology scaling and battery life in portable electronics, are accelerating the reduction in the supply voltage used for CMOS VLSI circuits beyond what might be expected from historical trends. While the scaling of transistor dimensions results in dramatic increases in both the speed and density of digital circuits, it also results in a corresponding increase in the electric fields within the device if the supply voltage is held constant. Breakdown considerations thus make it increasingly difficult to sustain the constant supply voltage that has characterized the past two decades of advances in CMOS technology. Moreover, lowering the supply voltage significantly reduces the energy consumed per operation in a digital system.