Performance analysis and VLSI design of a high-speed reconfigurable shared queue

Modern switches and routers require a large amount of storage space to buffer packets. This becomes more significant as the link speed increases and switch size grows. While DRAM is a good choice to provide capacity, the access time becomes a problem for high-speed applications. In this case, SRAM has to be used to match the link speed. However, SRAM is more costly and the density is low. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. -- To minimize packet loss and provide better quality of service (QoS), each switch port is normally equipped with a large amount of buffering resources, which is usually based on the worst case scenario. However, under normal load conditions, the buffer utilization is very low. Therefore, we propose a reconfigurable buffer sharing scheme in which a buffer controller can dynamically adjust the buffer size allocated for each port according to the parameters derived from the traffic pattern and buffer saturation status. The target is to improve the buffer utilization without posing much constraints on the buffer speed. -- In our research, we study how buffer sharing architectures improve the switch performance, based on the results from both numerical analysis and simulations. The performance results obtained from both uniform and nonuniform traffics demonstrate that the proposed reconfigurable shared buffer can provide better queuing performance with a much smaller shared buffer. We further conduct research into the VLSI design of the proposed reconfigurable shared queue architecture using hardware description language VHDL and using 0.18um CMOS technology. The design result indicates that the buffer sharing and control logic can be integrated into port controllers with a increasing of about 20,000 gate-count for each 4-port group, while the memory size can be reduced into half of the dedicated buffer scheme.