Comprehensive approach to MuGFET metrology

As we move forward to the 45 and 32nm node, MuGFET's (Multi-Gate Field-Effect Transistor) are considered more and more as a necessary alternative to keep pace with Moore's Law. If proven manufacturable, MuGFET's could eventually replace conventional CMOS transistors within a few years. The ability to perform proper and extensive metrology in a production environment is then essential. We investigate here some of the requirements of MuGFET metrology. Accuracy and line width roughness (LWR) metrology will play an essential role, because the small dimension of the features involved. 3D metrology is required when dealing with non-planar devices. Sophisticated check of optical proximity correction (OPC) is needed in order to ensure that the design is respected. We propose here some possible solutions to address the needs of MuGFET metrology in a production-worthy fashion. A procedure to calibrate CDSEM to TEM for accuracy is developed. We performed LWR metrology of fins in a fully automated way by using CDSEM, while the 3D information is obtained by means of scatterometry. Finally, we will discuss the application of design-based metrology (DBM) to MuGFET OPC validation.

[1]  Chris A. Mack Line Edge Roughness , 2006 .

[2]  W. Sansen,et al.  Line edge roughness: characterization, modeling and impact on device behavior , 2002, Digest. International Electron Devices Meeting,.

[3]  Luca Grella,et al.  Sub-50-nm isolated line and trench width artifacts for CD metrology , 2004, SPIE Advanced Lithography.

[4]  M. Ercken,et al.  Full spectral analysis of line width roughness , 2005, SPIE Advanced Lithography.