A monolithic CMOS 10 MHz DPLL for burst-mode data retiming

A first-order digital phase locked loop (DPLL) that can acquire phase lock from the highly jittered preamble of a burst-mode, Manchester-coded, 10-Mb/s data packet using information acquired from only three transistors is described. A 16-stage delay line locked to a 10-MHz reference clock is embedded in the DPLL. This allows 3.125-ns phase steps to be generated without a high-speed clock. Implemented in a 1.75- mu m CMOS technology, the DPLL circuit occupies 4 mm/sup 2/ of silicon and consumes 125 mW from a 5-V supply.<<ETX>>