A Roadmap for Formal Property Verification

1. Introduction. 1.1. Writing our First Formal Specification. 1.2. Is my specification correct? 1.3. Have I written enough properties? 1.4. Property Verification. 1.5. Verification by Specification Refinement. 1.6. The new flow. 2. Languages for Temporal Properties. 2.1. The basic temporal operators. 2.2. Logics for temporal specification. 2.3. System Verilog Assertions. 2.4. Architectural Styles for Assertion IPs. 2.5. Concluding Remarks. 2.6. Bibliographic Notes. 3. How does the property checker work? 3.1. Checkers are state machines! 3.2. The verification strategy. 3.3. Dynamic property verification. 3.4. Formal property verification. 3.5. BDD-based Formal Property Verification. 3.6. SAT-based Formal Property Verification. 3.7. Concluding Remarks. 3.8. Bibliographic Notes. 4. Is my specification consistent? 4.1. Satisfiability and Vacuity. 4.2. Satisfiability is not enough. 4.3. Games with the Environment. 4.4. Methods for Consistency Checking. 4.5. The SpecChecker Tool. 4.6. Concluding Remarks. 4.7. Bibliographic Notes. 5. Have I written enough properties? 5.1. Simulation Coverage Metrics. 5.2. Mutation-based FPV Coverage. 5.3. Structural versus Functional Coverage. 5.4. Fault-based FPV Coverage. 5.5. Concluding Remarks. 5.6. Bibliographic Notes. 6. Design Intent Coverage. 6.1. An Introductory Example. 6.2. The Formal Problem. 6.3. The Intent Coverage Algorithm. 6.4. Soundness of the Intent Coverage Algorithm. 6.5. Multi-property representation of the coverage gap. 6.6. SpecMatcher -- The Intent Coverage Tool. 6.7. Priority Cache Access -- A closer look. 6.8. Concluding Remarks. 6.9.Bibliographic Notes 7. Test Generation Games. 7.1. Constraint Random Test Generation. 7.2. Assertions viewed as Coverage Points! 7.3. Games with the Environment 7.4. Intelligent Test Generation for Property Coverage. 7.5. The Integrated Verification Flow. 7.6. Concluding Remarks. 7.7. BibliographicNotes. 8. A Roadmap for Formal Property Verification. 8.1. Simulation-based Validation Flow. 8.2. Formal Verification Flow. 8.3. The Three Pillars. 8.4. The Integrated Flow. 8.5. Sharing the Task. 8.6. Concluding Remarks. 8.7. Bibliographic Notes. 9. References

[1]  Pallab Dasgupta,et al.  Instruction-set-extension exploration using decomposable heuristic search , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[2]  Pallab Dasgupta,et al.  Syntactic transformation of assume-guarantee assertions: from sub-modules to modules , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[4]  Pallab Dasgupta,et al.  Abstractions for model checking of event timings , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[5]  Pallab Dasgupta,et al.  Multiobjective search in VLSI design , 1994, Proceedings of 7th International Conference on VLSI Design.

[6]  P. Dasgupta,et al.  A heuristic search approch to effectively solve constrained optimization problems from logical specifications , 1998 .

[7]  Ansuman Banerjee,et al.  Test generation games from formal specifications , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[8]  Pallab Dasgupta,et al.  A new method for transparent fault tolerance of distributed programs on a network of workstations using alternative schedules , 1997, Proceedings of 3rd International Conference on Algorithms and Architectures for Parallel Processing.

[9]  Pallab Dasgupta,et al.  Adaptive Algorithms for Scheduling Static Task Graphs in Dynamic Distributed Systems , 1999, HiPC.

[10]  Pallab Dasgupta,et al.  Abstraction of word-level linear arithmetic functions from bit-level component descriptions , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[11]  Pallab Dasgupta,et al.  Property Driven Test Generation in Absence of Direct Interface , 2006, 2006 Annual IEEE India Conference.

[12]  Ansuman Banerjee,et al.  Formal methods for analyzing the completeness of an assertion suite against a high-level fault model , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[13]  Pallab Dasgupta,et al.  Open computation tree logic for formal verification of modules , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[14]  P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .

[15]  Pallab Dasgupta,et al.  The BUSpec platform for automated generation of verification aids for standard bus protocols , 2004, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04..

[16]  Pallab Dasgupta,et al.  Timing Analysis of Sequential Circuits Using Symbolic Event Propagation , 2007, 2007 International Conference on Computing: Theory and Applications (ICCTA'07).

[17]  Ansuman Banerjee,et al.  Formal verification of module interfaces against real time specifications , 2002, DAC '02.

[18]  Ansuman Banerjee,et al.  CheckSpec: A Tool for Consistency and Coverage Analysis of Assertion Specifications , 2008, ATVA.

[19]  Krishnendu Chatterjee,et al.  Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures , 2004, IWDC.

[20]  Pallab Dasgupta,et al.  What lies between Design Intent Coverage and Model Checking? , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[21]  P. Dasgupta,et al.  Interactive Test-Bench Synthesis for Assertion-Based Verification , 2005, 2005 Annual IEEE India Conference - Indicon.

[22]  A. Banerjee,et al.  A dynamic assertion-based verification platform for UML statecharts over rhapsody , 2008, TENCON 2008 - 2008 IEEE Region 10 Conference.

[23]  Pallab Dasgupta,et al.  SAT based solutions for consistency problems in formal property specifications for open systems , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[24]  P.P. Chakrabarti,et al.  H-DBUG: A High-level Debugging Framework for Protocol Verification using Assertions , 2005, 2005 Annual IEEE India Conference - Indicon.

[25]  Ansuman Banerjee,et al.  Open computation tree logic with fairness , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[26]  Sayak Ray,et al.  A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[27]  Shuvendu K. Lahiri,et al.  Controlling state explosion in static simulation by selective composition , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[28]  Sayak Ray,et al.  Formal Verification of Power Scheduling Policies for Battery Powered Mobile Systems , 2006, 2006 Annual IEEE India Conference.

[29]  Pallab Dasgupta,et al.  Exploiting isomorphism for compaction and faster simulation of binary decision diagrams , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).