Forwarded-clock 수신기를 위한 Analog Front-end 설계

In this work, a front-end circuit for forwarded clock receiver is proposed. The front-end circuit contains a CTLE and a clock buffer which operate at 25Gb/s and 6.25GHz, respectively. Since the degeneration resistor and capacitor of CTLE are controllable, the peak gain and DC gain can be changed. To reduce the power dissipation and set the common level, the clock buffer is designed by using inverter chains and resistive feedback.