Behavioral simulation of a 3-bit flash ADC

A behavioral-level simulation of a 3-b flash analog-digital converter (ADC) is presented. This application illustrates the usefulness of higher-level modeling of analog circuits. Such models allow efficient simulation of analog or mixed analog-digital systems while providing meaningful results. This particular example illustrates how comparator delays affect the functionality of a flash ADC and how behavioral-level simulation can preserve this information.<<ETX>>

[1]  I.E. Getreu,et al.  An integrated-circuit comparator macromodel , 1976, IEEE Journal of Solid-State Circuits.

[2]  J. Solomon,et al.  Macromodeling of integrated circuit operational amplifiers , 1974 .

[3]  I. M. Wilson.  Analog behavioral modeling using PSPICE , 1989, Proceedings of the 32nd Midwest Symposium on Circuits and Systems,.

[4]  I. E. Getreu.  Behavioral modeling of analog blocks using the Saber simulator , 1989, Proceedings of the 32nd Midwest Symposium on Circuits and Systems,.

[5]  A. Jimenez,et al.  Algorithms for ASTAP--A network-analysis program , 1973 .

[6]  H.A. Mantooth,et al.  A behavioral model of an analog voltage comparator , 1989, Proceedings of the 32nd Midwest Symposium on Circuits and Systems,.