High speed and low power ADC design with dynamic analog circuits

This paper discusses high speed and low power ADC design with dynamic analog circuits. An OpAmp based ADC design is no longer useful in nano-meter CMOS era and a comparator based ADC design becomes dominant for ADC design along with technology scaling. Offset mismatch and input referred noise in a comparator affects ENOB seriously. Furthermore conversion speed, energy consumption and occupied area have a serious tradeoff in ENOB. A digital offset mismatch compensation technique accommodates this trade off, however accuracy is not sufficient and more effective technique should be developed. An equation to estimate the input referred noise in dynamic comparator has been deduced and it suggests that the noise can be reduce by increase of load capacitance and reduction of the effective gate voltage. However higher resolution than 10 bit looks not easy. Technology development is required to realize higher resolution ADC1.