Estimating testing effectiveness of the circular self-test path technique
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[1] Dong Sam Ha,et al. On using signature registers as pseudorandom pattern generators in built-in self-testing , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Paul H. Bardell,et al. Self-Testing of Multichip Logic Modules , 1982, International Test Conference.
[3] René David. Comments on "Signature Analysis for Multiple Output Circuits" , 1990, IEEE Trans. Computers.
[4] Michael H. Schulz,et al. Improved deterministic test pattern generation with applications to redundancy identification , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] C.E. Stroud,et al. Automated BIST for sequential logic synthesis , 1988, IEEE Design & Test of Computers.
[6] Amitava Majumdar,et al. Test efficiency analysis of random self-test of sequential circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] André Ivanov,et al. An analysis of the probabilistic behavior of linear feedback signature registers , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Edward J. McCluskey,et al. Pseudorandom Testing , 1987, IEEE Transactions on Computers.
[9] A. Krasniewski,et al. Effectiveness of fault detection for low-overhead self-testing VLSI circuits , 1988, 1988., IEEE International Symposium on Circuits and Systems.
[10] M. M. Pradhan,et al. Circular BIST with partial scan , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[11] The Challenges of Self-Test , 1990, IEEE Des. Test Comput..
[12] Michele Favalli,et al. An analytical model for the aliasing probability in signature analysis testing , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[13] Jacob Savir,et al. On Random Pattern Test Length , 1984, IEEE Transactions on Computers.
[14] W. Daehn,et al. Aliasing errors in multiple input signature analysis registers , 1989, [1989] Proceedings of the 1st European Test Conference.
[15] Vishwani D. Agrawal,et al. A Statistical Theory of Digital Circuit Testability , 1990, IEEE Trans. Computers.
[16] F. Brglez,et al. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .
[17] B. Koenemann,et al. Built-in logic block observation techniques , 1979 .
[18] Prab Varma,et al. An Analysis of the Economics of Self Test , 1984, ITC.
[19] Charles E. Stroud,et al. An automated BIST approach for general sequential logic synthesis , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[20] B. Ricco,et al. Aliasing in signature analysis testing with multiple-input shift-registers , 1989, [1989] Proceedings of the 1st European Test Conference.
[21] Thomas W. Williams,et al. Design for Testability - A Survey , 1982, IEEE Trans. Computers.
[22] Jacob Savir,et al. Built In Test for VLSI: Pseudorandom Techniques , 1987 .
[23] Andrzej Krasniewski,et al. Circular self-test path: a low-cost BIST technique for VLSI circuits , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[24] Wilfried Daehn,et al. Bounds and analysis of aliasing errors in linear feedback shift registers , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..