An on-chip power modulator

We report our results on pulse forming line (PFL) based CMOS pulse generator studies. Standard on-chip transmission lines are used as PFLs while CMOS transistors are used as switches. Through simulations, we clarify the effects of switch speed and switch resistance on the generated pulses. In a standard 0.13 μm CMOS process with a 500 μm long PFL, post layout simulations show that pulses of 10.4 ps width can be obtained. Thus, the PFL circuit significantly extends short pulse generation capabilities of CMOS technologies. Much shorter pulses can be generated with more advanced digital CMOS processes and silicon germanium (SiGe) BiCMOS technologies. A CMOS circuit with a 4 mm long PFL is implemented in a commercial 0.13 μm CMOS technology. Pulses of ∼ 160 ps duration and 120–180 mV amplitude on a 50Ω load are obtained when the power supply is tuned from 1.2 V to 2.0V. Possible reasons for low output voltage and long pulse width include measurement instrument limitations and parasitic effects.

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