VLSI Design for Reliability-Hot Carrier Effects

Abstract : This report describes the accomplishments during the contract period (June 28, to June 27, 1992) on the computer aided analysis of CMOS device and circuit degradation due to hot-carrier effects. The task involved four subtasks: (1) simulation of gate oxide degradation during long-term circuit operation; (2) determination of overall circuit performance after hot-electron stress; (3) probabilistic timing approach to hot-carrier-effect estimation; (4) parametric macromodeling of hot-carrier-induced degradation in MOS VLSI circuits. The first two parts are continued subtasks while the latter two are new subtasks. In order to simulate the reliability of MOS circuits, both the detailed model and the macromodel are used; the detailed model is used for accurate analysis of small circuits and the macromodel is used for very large circuits for computational efficiency. Since the hot-carrier-induced aging of MOS circuits is input-pattern dependent, an important task is to develop a computationally efficient probabilistic timing approach to hot-carrier-effect estimation without resorting to the Monte Carlo simulation. We have developed a new probabilistic approach that accounts for cumulative effects of all input waveform combinations in a single run. VLSI reliability, Hot-carrier effects, Computer aided design.